work needs to read make recently
there is an example in the official GNU make document that I don"t quite understand, and some friends who understand it want to give an answer.
is as follows: Makefile:

objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)
main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit $(objects)
        

is modified as follows in the next section:

objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY : clean
clean :
        rm edit $(objects)

look at the official document that there are implicit rules? Excuse me?
the official manual is as follows:

It is not necessary to spell out the recipes for compiling the individual C source files, because make can figure them out: it has an implicit rule for updating a".o "file from a correspondingly named" .c "file using a" cc-c "command. For example, it will use the recipe"cc-c main.c-o main.o" to compile main.c into main.o. We can therefore omit the recipes from the rules for the object files. See Using Implicit Rules.When a".c "file is used automatically in this way, it is also automatically added to the list of prerequisites. We can therefore omit the".c "files from the prerequisites, provided we omit the recipe.