ISE synthesis passed, but wrong in layout and cabling times - Codes Helper

ISE calls IP core ram. Syntax and synthesis are passed, and port instantiation is correct, but

is displayed during layout and routing.

File "ipcore_dir/ram_test.ngc" cannot be merged into block "Instant_ram_test_1" (TYPE= "ram_test") because one or more pins on the block, including pin "wea", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention. (the file "ipcore_dir / ram_test.ngc" cannot be merged into the block "Instant_ram_test_1" (TYPE = "ram_test") because one or more pins in the block (including pin "wea") were not found in the file. Make sure that all pins on the instantiated component match the pins in the lower-level design module (regardless of the situation). If there are bus pins on this block, make sure that the upper and lower Netlist use the same bus naming convention.)

code is as follows:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity test_bram_memory is
    port (
        data_in    :     in  STD_LOGIC_VECTOR (63  downto 0);
        wr_en        :     in  STD_LOGIC;    
        clk         :  in  STD_LOGIC;
        addr        :     in  STD_LOGIC_VECTOR (16 downto 0);
        rst_n        :     in  STD_LOGIC;
        ena        :    in  STD_LOGIC;
        data_out    :     out STD_LOGIC_VECTOR (63 downto 0);
        data_en     :     out STD_LOGIC
    );
end test_bram_memory;

architecture Behavioral of test_bram_memory is

    COMPONENT ram_test IS 
    port(
        clka        :  in  STD_LOGIC;   
        wea        :    in  STD_LOGIC;
        dina        :     in  STD_LOGIC_VECTOR (63  downto  0);
        addra        :     in  STD_LOGIC_VECTOR (16 downto  0);
        ena        :    in  STD_LOGIC;
        rsta        :  in  STD_LOGIC;
        douta        :  out STD_LOGIC_VECTOR (63  downto  0)
    );
    END COMPONENT;
    
begin
    
    process (clk, rst_n)
    begin
        if (rst_n = "0") then 
            data_en <= "0";
        elsif (falling_edge(clk)) then
            data_en <= wr_en;
        end if;
    end process;

Instant_ram_test_1    : ram_test  port map (
    clka     =>     clk,
    wea     =>     wr_en,
    dina     =>     data_in,
    addra =>     addr,
    ena    =>     ena,
    rsta  =>      rst_n,
    douta =>     data_out
);

END Behavioral;

ask the boss for help, thank you